The invention relates generally to semiconductor integrated circuit (IC) devices and more particularly, it relates to buck converters.
Buck converters are used to convert a higher voltage to a lower voltage suitable for use with, for example, a microprocessor. A buck converter typically operates using a clock, whereby an inductor is charged during a first portion of a clock cycle (xe2x80x9ccharging phasexe2x80x9d) and operates as a current source during the second portion of the clock cycle (xe2x80x9cdischarging phasexe2x80x9d). Recently, buck converters have evolved into multi-phase buck regulators. A conventional multi-phase buck converter allows multiple low currents to be delivered via the multiple phases respectively. The sum of the inductor currents is provided as an output. Such a conventional multi-phase converter suffers from a serious drawback in that the different phases must not overlap each other. Otherwise, the controller cannot distinguish among the inductor currents generated, resulting in unstable or ineffective control. Non-overlapping phases result in much slower response time for high current output. Therefore, a conventional multi-phase converter generally cannot include more than a few phases.
Conventional multi-phase converters also suffer from the limiting factors associated with the discrete implementation, including response time, efficiency and cost. Response time is generally longer in discrete circuits due to large distances between the discrete circuit components, which result in a large time constant. Low efficiency is also associated with discrete circuits because of high switching losses. Discrete circuits are also more expense than integrated circuits.
Therefore, there is a need for an improved buck converter with superior performance.
The present invention provides a solution that addresses all of the limiting factors in the discrete buck converter. According to one embodiment of the invention, an n-phase integrated buck converter is provided and comprises a controller and a plurality of circuits each operably connected to the controller. The controller and the plurality of circuits are integrated. The controller generates a plurality of drive signals to control the plurality of circuits respectively, the plurality of drive signals each having an associated phase.
According to one aspect of the invention, the plurality of circuits generate a plurality of current signals respectively and an output voltage signal.
According to another aspect of the invention, the output voltage signal is fed back to the controller. The controller comprises a duty cycle control circuit that compares the fed-back output voltage signal with a pre-selected reference voltage and adjusts a duty cycle value of the drive signals based on the comparison to maintain the output voltage signal at a desired level.
According to a further aspect of the invention, a sum of the plurality of current signals is fed back to the controller. The duty cycle control circuit compares the sum of the fed-back current signals with previous value of the sum and adjusts a duty cycle value of the drive signals based on the comparison to maintain the output voltage signal at a desired level.
By applying the n phase concept of the invention, the amount of current each phase (i.e., each of the plurality of circuits) has to deliver is reduced. This directly reduces the conduction losses in each phase. Because the current in each phase is lower, a smaller MOSFET in each of the plurality of circuits may be used. The smaller MOSFET is easier to switch. Therefore, the switching losses per phase are also reduced. Reducing these losses will enable the invention to achieve efficiencies greater than the discrete solution since 90% of the losses in the conversion process are located in the MOSFETs.
According to the invention, the response time is shortened by integrating the controller with the power train (i.e., PMW drivers and MOSFETs). This integration reduces the parasitic inductances and capacitances that limit the converter""s ability to respond quickly. Integration allows all of the components to become physically closer and capable of being switched faster. Faster switching frequencies allow for smaller and less passive components. Integration also minimizes the total cost of the converter.
Increasing the switching frequency of the converter not only shortens response time but also reduces the size of the output inductors required by the buck topology. It may be possible to increase the frequency of the converter to such a point that discrete output inductors are no longer required but that the inductance of the package itself may replace them.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.